We have started collecting "Nano Nuggets"- useful bits of information about different processing methods that should be extremely helpful either in getting started or avoiding pitfalls along the way. Some of them are parts of more detailed project reports, so if you want more info about a nugget, the report should be linked. Check them out!
Tips for wet etching of glass substrates with resist adhesion problems.
Our goal was to develop a process for sputtering of NVM-quality TiN using the new Lesker sputtering tool (Lesker-2) that resides inside the cleanroom. This tool can achieve the high-vacuum pressures necessary for TiN films with low levels of oxygen contamination.
The nanoscribe can be used to create template structures for particle self assembly, and details about inverse opal BCC and FCC structures are described.
The basic version of the Standard Operating Procedures for this tool is already available online but we propose a modified version that ensures higher yield of successful releasing and better overall cleanliness of the process on small chips:
We worked out a method for releasing niobium structures with high yield.
Procedures for troubleshooting post Nb-etch residues on Sapphire wafers are described.
This document contains standard operating procedures (SOPs) for the following processes: 1.Fabrication of oxide hard mask for deep silicon etching. 2.Tapered etch method for blade formation using PT-DSE 3.Through-hole etching using PT-DSE
An improved substrate pretreatment protocol is therefore developed that results in better adhesion.
Tips for deposition of very thin, low temperature Al2O3 in the Savannah in the SNF.
Both electrical and physical characterization techniques are explained for characterizing thin ALD films.
Some processing details for printing patterns for silicon nanowire fabrication.
Procedures for doing NIL in preparation for MACE etching.
Procedures for doing MACE etching to make tall pillars in silicon.
Standard operating procedures for seed layer aided ALD on 2D materials.
Process to create electrical test structures using metal-seeded ALD layers on silicon substrates.
A two stage etching procedure can be used to fabricate various vertical nanostructures for bio-relatedexperiments.